Conifer turns boosted trees into FPGA firmware for low-latency inference

If your model is a boosted decision tree and your inference budget is measured in clock cycles rather than milliseconds, Conifer targets that constraint directly. It takes a trained tree ensemble and emits firmware projects for FPGA deployment, instead of running the model on a CPU or GPU and accepting the associated latency and jitter. The project originated in particle physics work, where trigger decisions must be made in hardware with deterministic timing. It grew out of hls4ml and is developed under the Fast Machine Learning Lab. A peer-reviewed paper in JINST describes the approach, and the repository links to API documentation, examples, and a tutorial section in the hls4ml tutorial. That lineage matters for builders: this is not a generic model exporter, it is a toolchain shaped by a specific hardware deployment problem. Converters and backends Input support covers the frameworks most teams already train with. Conifer lists converters for scikit-learn, XGBoost, ONNX, TMVA, and ydf. The ONNX path is the practical route for LightGBM and CatBoost models via ONNXMLTools. On the output side, the choice of backend determines how much of the toolchain you need to install and how portable the result is. Xilinx HLS: emits an HLS project for synthesis with Vitis HLS or Vivado HLS, whichever is on your PATH. The README recommends a recent Vivado ML and Vitis HLS, with 2024.1 as the latest validated version. VHDL: a direct-to-VHDL implementation described as deeply pipelined for high clock frequencies, with ModelSim and GHDL supported for simulation. FPU: a Forest Processing Unit IP core that can be programmed for different BDTs without rebuilding the IP or bitstream, useful when the hardware must stay fixed while models change. C++ and Python: CPU-side backends for bit-accurate emulation and model inspection before you commit to synthesis. Installation is pip install conifer, but firmware builds add real dependencies. C++ backends need JSON headers and Xilinx arbitrary-precision headers such as ap_fixed.h, located via JSON_ROOT and XILINX_AP_INCLUDE if you are not using a sourced Vivado installation. Precision is part of the configuration, for example setting Precision to ap_fixed in the auto-generated Xilinx